The invention relates to an integrated memory circuit, comprising an erasable programmable memory comprising a generator for generating a programming voltage for the memory, which generator comprises a charge pump and at least one of the following controllers: a voltage controller for limiting the programming voltage, and an edge controller for limiting an increase of the programming voltage per unit of time.
The invention also relates to a generator for generating a programming voltage for the memory, and a voltage controller and an edge controller, both suitable for use in such a generator. A memory circuit and a generator comprising a voltage controller and an edge controller, all of the kind set forth, are known from Netherlands Patent Application 8400225. As is described therein, excessively high programming voltages as well as an excessively high speed at which the programming voltage cross the memory increases are detrimental to the programmable memories (EPROM, EEPROM). In order to mitigate these drawbacks, a state of the art memory circuit is constructed as follows. In series with a charging resistance, a parallel arrangement of the memory on the one side and the edge controller on the other side is inserted between connections of the charge pump. The edge controller comprises a parallel arrangement of a controllable current channel which includes a current channel of a large field-effect transistor, and a series connection of a current channel of a small field-effect transistor with a capacitance. The control electrodes of the large and the small transistor are connected to a junction point between the small transistor and the capacitance. When the charge pump is activated, initially the bulk of the current will be dissipated via the controllable current channel, without contributing to an increase of the programming voltage for the memory. As a small current through the small transistor charges the capacitance further, the current through the large transistor decreases and the voltage across the memory increases. The edge steepness at which this programming voltage increases is codetermined by the dimensions of the transistors and the magnitude of the capacitance. The value of the maximum programming voltage is codetermined by the ratio of the charging resistance and the leakage resistance of the memory, which resistances constitute a voltage divider. Even though this set-up is simple, the known memory circuit can be improved. First of all, the known memory circuit dissipates additional power because the charging current generated by the charge pump initially does not benefit the programming voltage. Secondly, the maximum value of the charging voltage and the edge steepness realized are also dependent on the power delivered by the charge pump. This implies that the charge pump, the charging resistance, the memory and the edge controller must be adapted to one another.